Flash memories, which are non-volatile memories, are generally classified into NAND flash memories and NOR flash memories. Since the NAND flash memories are superior to the NOR flash memories in terms of degree of integration, a NAND structure is mainly used in high-density flash memories. In general, the NAND flash memories include a cell array, a column decoder, and a page buffer. The cell array may include a data cell array for data, a spare cell array, and a redundant cell array for replacing a defective data cell or spare cell.
A test may be performed to check whether such a non-volatile memory operates normally. In the case where a test result indicates the occurrence of a failure in a portion of data cell arrays, a redundant cell array may perform a function of a data cell array in which the failure has occurred, instead of the data cell array.
A NAND flash memory performs a program operation on a page-by-page basis. Therefore, a page program operation is repetitively performed to perform the above-mentioned test. In detail, in order to program one page, a “page program command (e.g., 90h)”, a “page address”, “program data”, and a “program start command (e.g., 10h)” are sequentially input. Therefore, in order to program an entire chip in this manner, the page program command should be repeated for all page addresses.
Furthermore, in order to perform erase/program cycling, a page program for the entire chip or a specific block and a block erase process in which a “block erase command (e.g., 60h), a “block address”, and an “erase start command (e.g., D0h)” are sequentially input to erase a block may be repetitively performed.